1. Field of the Invention
The present invention relates to electronic devices, and particularly semiconductor digital potentiometers.
2. Description of the Related Art
Various types of digital potentiometers for providing variable resistance have been known. Specifically, digital potentiometers are typically comprised of a resistor array with a plurality of selectable tap points electronically connected to a common terminal or "wiper." For each selectable tap point, there is a corresponding semiconductor gate device for switching a signal path through the gate device and into the resistor array at the specified tap point. semiconductor gate device for switching a signal path through the gate device and into the resistor array at the specified tap point.
Known digital potentiometers suffer from shortcomings, namely, they require electrical power to maintain their electrical characteristics. Inventions for resetting such electrical characteristics after a power outage have been proposed to compensate for this shortcoming. For example, Drori U.S. Pat. No. 4,668,932 and Zanders U.S. Pat. No. 5,717,935 have been proposed to use nonvolatile memory for storing and retrieving a value corresponding to a certain tap point (Drori) or control value (Zanders) of a potentiometer. When the power is restored Drori and Zanders retrieve a value from memory and use that value to reset the potentiometer's pre-outage electrical characteristics. These inventions employ variations of a technique which has long been familiar in the memory art, shadow RAM, where volatile memory is used for the primary memory, and a nonvolatile memory is used to backup the volatile memory.
There are at least three significant shortcomings to using shadow RAM. First, the technique merely restores what has been lost and does not prevent the loss from occurring. This shortcoming is particularly apparent in applications where power is or may be intermittent (e.g., in wireless phones and Personal Digital Assistants). Second, known digital potentiometers consume power while simply maintaining a wiper position, a waste of energy particularly where energy conservation is critical, as in, for example, battery-powered portable electronic equipment. Third, the technique employs recovery processes that require a recovery time which, depending on the application, may cause intolerable delays.
In these regards, the inventors herein have made a substantial improvement over the Drori, Zanders systems or other shadow RAM systems by using nonvolatile memory cells, not for storing a value, but for providing a static, nonvolatile power source to the potentiometer.
Examples of these improvements are evident in embodiments using a nonvolatile semiconductor memory cell which has not to the inventor's knowledge been used so as to provide power to a digital potentiometer, an EEPROM memory cell. The central part oaf classic EEPROM cell is typically a floating-gate transistor, i.e., a MOS transistor which has two gates stacked on top of each other, so that the two gates are capacitively coupled to each other and to a channel. One gate is called a "floating" gate, because it is electrically isolated. By injecting charges into the floating gate, the effective threshold voltage of the MOS transistor (as seen from the other gate) can be changed. This electrically isolated charge endures independently from the semiconductor's primary, volatile energy source.
In a preferred embodiment of the present invention, this isolated electrical source provides a constant charge for maintaining a selected resistance. In setting or unsetting the wiper to or from a given tap position, the floating gate of a corresponding nonvolatile memory cell, e.g., an EEPROM memory cell, is set by an electrical charge which, in turn, activates or deactivates an adjacent transistor which, in turn, forms or unforms a conductive channel between the corresponding wiper point in the resistor array and an output line. When a selected resistance is set, it is maintained statically by the isolated electrical field of the corresponding memory cell for as long as the corresponding memory cell maintains its setting regardless of power to the remainder of the circuitry.